ifos • paper_2 • solid_state_electronics
[UPSC IFoS 2010] Digital Electronics/Microprocessors (Q333, 10M)
Employing NAND gates, design a half adder circuit which can add two bits A and B and provide a sum S and a carry C as its output.
Employing NAND gates, design a half adder circuit which can add two bits A and B and provide a sum S and a carry C as its output.
Discussion (0)
Sign in to post a solution, derivation, or discussion.
No comments yet. Start the conversation!